User`s guide

XMI Registers
Bus Error Register (XBER)
bit<29>
Name: Node Halt
Mnemonic: NHALT
Type: R/W, 0
Writing a one to NHALT forces the node to go into a "quiet" state
while retaining as much state as possible. The CPU halts and goes
into console mode waiting for console commands.
bit<28>
Name: XMI BAD
Mnemonic: XBAD
Type: R/W, 1
On reads, XBAD indicates the state of the XMI BAD signal. A one
indicates that BAD is asserted. Writes to this location supply the
state to be driven on the wired-OR XMI BAD L line by this node;
writing a one asserts XMI BAD L, while writing a zero releases it.
Only XMI processor nodes are required to implement this bit. If not
implemented, nodes return zero.
bit<27>
Name: Corrected Confirmation
Mnemonic: CC
Type: R/W1C, 0
CC sets when the node detects a single-bit CNF error. Single-bit CNF
errors are automatically corrected by the XCLOCK chip.
bit<26>
Name: XMI Trigger
Mnemonic: XTRIG
Type: R/W1C, 0
Represents the state of the XMI TRIGGER line and is used by Digital
during hardware development.
bit<25>
Name: Write Error Interrupt
Mnemonic: WEI
Type: R/W1C, 0
When set, WEI indicates that the node has received a write error
interrupt transaction. Only XMI processor nodes are required to
implement this bit. If not implemented, nodes return zero.
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