User`s guide

Contents
3.13.3 DWMBB/B Module Initialization Sequence 3–132
3.14 DIAGNOSTIC FEATURES 3–133
3.14.1 Internal Loopback Modes 3–134
3.14.1.1 DWMBB/A Module Loopback • 3–134
3.14.1.2 BIIC Loopback • 3–135
3.14.1.3 DMA Loopback • 3–136
3.14.2 DWMBB/A Module Gate Array Transaction Register Files
Testing 3–137
3.14.2.1 Executing DMA Writes and Reads in Loopback Mode • 3–141
3.14.2.2 Transaction Register File in Loopback Mode Using DMA Writes
and Reads • 3–143
3.14.3 Forcing Bad Parity 3–145
3.14.3.1 Forcing Bad Parity on the IBUS • 3–145
3.14.3.2 Forcing Bad Parity on the BCI • 3–146
3.14.4 ECC and the ECC RAMs Testing 3–146
3.14.5 XMI Lockout Testing 3–147
3.14.6 Timeout Testing 3–147
3.14.7 Control Reset 3–147
3.14.8 Diagnostic Read/Write Registers 3–148
3.14.9 Miscellaneous Diagnostic Bits 3–148
3.14.10 Error Conditions in Diagnostic Modes 3–149
CHAPTER 4 POWER AND COOLING SYSTEMS 4–1
4.1 POWER SYSTEM 4–1
4.1.1 Input Power 4–2
4.1.2 H7206-B Power and Logic Unit 4–2
4.1.3 H7214 Power Regulator 4–3
4.1.4 H7215 Power Regulator 4–3
4.1.5 H7242 Power Regulator 4–3
4.1.6 XTC Power Sequencer 4–3
4.1.6.1 XMI Reset Timing Control Logic • 4–3
4.1.6.2 TOY Circuits • 4–3
4.1.6.3 Console Line Driver and Receiver • 4–4
4.1.7 Power System Signals 4–5
4.1.8 H7236-A Battery Backup Unit 4–6
4.2 COOLING SYSTEM 4–7
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