User`s guide

XMI Registers

Bus Error Register (XBER)

bit<31>

Name: Error Summary

Mnemonic: ES

Type: RO, 0

ES represents the logical OR of the error bits in this register.

Therefore, ES asserts when one or more of the following error bits

assert.

XBER Bit Mnemonic Name

<27> CC Corrected Conﬁrmation

<25> WEI Write Error Interrupt

<24> IPE Inconsistent Parity Error

<23> PE Parity Error

<22> WSE Write Sequence Error

<21> RIDNAK Read/IDENT Data NO ACK

<20> WDNAK Write Data NO ACK

<19> CRD Corrected Read Data

<18> NRR No Read Response

<17> RSE Read Sequence Error

<16> RER Read Error Response

<15> CNAK Command NO ACK

<13> TTO Transaction Timeout

bit<30>

Name: Node Reset

Mnemonic: NRST

Type: R/W, 0

Writing a one to NRST initiates a complete power-up reset similar to

the assertion and deassertion of XMI DC LO L (see note below); the

node performs self-test and asserts XMI BAD L until it is successfully

completed. Like power-up reset, nodes are precluded from accessing

the node from the time it is node reset until it completes self-test (or

the maximum self-test time is exceeded).

NOTE: During the time that a node is responding to node reset, the

node does not access other nodes on the XMI bus. In response

to a real power-up sequence (caused by XMI DC LO L), the

NRST bit will be reset. Following a node reset sequence, it will

remain set allowing the processor to recognize that it should

not attempt to go through the normal boot process.

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