User`s guide

The XMI
2.6 Cache Coherency
All cache-resident nodes monitor bus traffic to remain consistent.
XMI processors never generate memory references between an
Interlock Read and the corresponding Unlock Write.
Caches are high-speed local memory subsystems residing between the
processor and main memory. Cache control logic maintains the local copies
of data likely to be used by the processor. This reduces the effective access
time to memory, since a percentage of the processor references are serviced
quickly by the local memory.
The VAX 6000 uses two different cacheing schemes: writeback and write
through. Cache schemes are CPU specific and are described in the System
Technical User’s Guide for each CPU in the VAX 6000 series family.
2–52