User`s guide

Contents
3.12.3 Multiple Errors 3–115
3.12.4 Address Translation Mode Errors 3–115
3.12.4.1 Invalid VAXBI Address • 3–116
3.12.4.2 Invalid PFN • 3–116
3.12.4.3 ECC Errors on PMR Data During DMA Address
Translation • 3–117
3.12.4.3.1 Uncorrectable ECC Errors • 3–117
3.12.4.3.2 Correctable ECC Errors • 3–117
3.12.4.4 ECC Errors on PMR Data During I/O Reads to PMR • 3–118
3.12.4.4.1 Uncorrectable ECC Errors • 3–118
3.12.4.4.2 Correctable ECC Errors • 3–118
3.12.5 IBUS Parity Errors 3–119
3.12.5.1 DMA Write C/A or INTR C/A IBUS Parity Error • 3–119
3.12.5.2 DMA Write Data IBUS Parity Error • 3–119
3.12.5.3 DMA Read C/A IBUS Parity Error • 3–120
3.12.5.4 I/O Read Data or IDENT Vector IBUS Parity Error • 3–120
3.12.5.5 DMA Read Data IBUS Parity Error • 3–120
3.12.5.6 I/O Write C/A IBUS Parity Error • 3–121
3.12.5.7 I/O Write Data IBUS Parity Error • 3–121
3.12.5.8 I/O Read C/A IBUS Parity Error • 3–121
3.12.5.9 IDENT IBUS Parity Error • 3–122
3.12.5.10 Undecodable I/O C/A with no IBUS Parity Error
Detected • 3–122
3.12.5.11 Undecodable DMA C/A with no IBUS Parity Error
Detected • 3–123
3.12.5.12 Undecodable DMA C/A with an IBUS Parity Error
Detected • 3–123
3.12.6 XMI Errors 3–124
3.12.6.1 DMA Write C/A XMI Error • 3–125
3.12.6.2 DMA Read C/A XMI Error • 3–125
3.12.6.3 DMA Write Data XMI Error • 3–125
3.12.6.4 DMA Read Data XMI Error • 3–125
3.12.6.5 Parity Errors on the XMI • 3–126
3.12.6.6 I/O Read Data and IDENT Vector Errors on the XMI • 3–126
3.12.6.7 I/O Write Data Error on the XMI • 3–126
3.12.6.8 LOC Response on DMA Read Data • 3–126
3.12.7 VAXBI Errors 3–127
3.12.8 Miscellaneous Errors 3–128
3.12.8.1 Impending Power Fail • 3–128
3.12.8.2 Internal Errors • 3–128
3.12.8.3 PMR Initialization Inhibit Error • 3–128
3.12.8.4 DMA Read Data Parity Error during DWMBB/A Module
Loopback • 3–129
3.12.8.5 Cable OK Error • 3–129
3.13 DWMBB INITIALIZATION 3–130
3.13.1 DWMBB/A Module Initialization Sequence 3–131
3.13.2 DWMBB/A Module Gate Array Control Reset 3–131
viii