User`s guide

The XMI
The four multiple quadword Read transactions move either 16 bytes
(octaword) or 32 bytes (hexword) of data from the responder to the
commander. Figure 2–26 is the command transfer of the transaction.
The Interlock Read checks the state of the ownership and lock bits in the
memory and qualifies the request, based on their state. This illustration
applies to both octaword and hexword reads.
Figure 2–27 is a diagram of the return data transfer applicable to octaword
reads. The function field of the bus in cycle 1 indicates "good read data
0" with the ID field identifying the intended receiver (the transaction
commander). Cycle 4 is a Good Read Data 1 cycle. Each cycle provides a
new quadword of read data while the ID remains unchanged.
Read data may be returned in consecutive cycles through the use of HOLD,
as shown in Figure 2–28. The transmitter asserts HOLD in the first cycle
to ensure that it maintains the use of the bus until it completes the
transfer. HOLD is the highest priority arbitration line and guarantees use
for a maximum of four consecutive cycles. The confirmation is returned to
the commander two cycles after the command cycle.
Bus usage during a hexword read with a single correctable read error is
shown in Figure 2–29.
Figure 2–30 illustrates the events during a return data of hexword length
containing an uncorrectable read error. When memory encounters an
uncorrectable read error, it returns a Read Error Response and suppresses
further read responses for that transaction.
Figure 2–29 Hexword Read with Single Correctable Read Error
01234567
FUNCT
DATA
ID
CONF
ARB
|
|
|
|
|GRD0|GRD1|CRD2|
|DAT0|DAT1|DAT2|
|CMDR|CMDR|CMDR|
|GRD3|
|DAT3|
|CMDR|
|
|
|
|
|
|
| |ACK |ACK |ACK |
|RESP| ||RESP|HOLD|HOLD|
| |ACK |
|
msb−p181−89
|
2–49