User`s guide

The XMI
2.5.10 Implied Vector Interrupt Transactions
The Implied Vector Interrupt (IVINTR) is a single-cycle transfer used
to implement VAX interprocessor interrupts and write error interrupts
where the interrupt priority and interrupt vector are implied by the type
of interrupt (see Figure 2–23).
Figure 2–23 Implied Vector Interrupt Command
6
3
6
0
5
9
2
0
1
9
1
8
1
7
1
6
1
50
Reserved NODE ID
Reserved
Reserved
WRITE ERROR INTERRUPT
1111
IVINTR COMMAND
msb−p196−89
INTERPROCESSOR INTERRUPT
INTERRUPT DESTINATION
Interprocessor interrupts are issued at IPL 16 (hex) with a vector of 80
(hex). Write error interrupts are issued at IPL 1D (hex) with a vector of 60
(hex). Since the value of the interrupt vector is indicated by the value of
the Type field, IVINTR transactions do not require a corresponding IDENT
(identify or interrupt acknowledge cycle).
The IVINTR transaction contains a 4-bit Type field used to specify the
type of interrupt. Only two bits are used: <16> specifies an interprocessor
interrupt, while <17> specifies a write error interrupt. These bits are
mutually exclusive. The IVINTR transaction also contains a 16-bit
Node Specifier field (one bit per node) indicating which nodes are to be
interrupted. Interprocessor interrupt transactions can be directed to more
than one node. Write error interrupt transactions are directed to only one
node. The XMI FAULT signal can be used to signal an error to multiple
nodes.
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