User`s guide

The XMI
2.5.9 Interrupt and Identify Transactions
Any I/O device can send an interrupt to one or more processor nodes. A
processor eventually issues an IDENT and then performs the necessary
service routine.
Each processor on the XMI has the capability of handling 64 interrupts,
one interrupt for each of the four interrupt priority levels (IPLs) for each
of the 16 possible XMI nodes.
Any I/O adapter on the XMI can send out an Interrupt (INTR) transaction
to one or more CPU nodes, as designated by a destination mask. One
of the processors eventually issues an Identify (IDENT) transaction at
a selected level <7:4> and chooses one interrupting node to send it to.
That processor then clears that I/O interrupt-pending flag, but other
I/O interrupts (if any) wait to maintain the CPU interrupt request. An
interrupt vector is eventually sent to the CPU that issued the IDENT.
This CPU then performs the interrupt service routine.
If an interrupting node issues multiple interrupts each at a different
IPL, it need not reissue the outstanding interrupts after one has been
serviced. Each CPU monitors the XMI for IDENTs issued by another
node. An IDENT issued by one CPU to an interrupting device causes
the other processor nodes to clear their corresponding interrupt-pending
flag. An interrupting node is not allowed to have more than one interrupt
outstanding at a given level.
If more than one processor issues an IDENT for the same interrupt, the
first processor node to win the XMI processes the interrupt and the other
CPUs clear their corresponding interrupt-pending flags and abort the
IDENT.
The Interrupt command is shown in Figure 2–20; the Identify command
is shown in Figure 2–21; and the Identify response (Good Data Read
Response—function code of 1000) is shown in Figure 2–22.
Figure 2–20 Interrupt Command
6
3
6
0
5
9
4
8
4
7
3
2
3
1
2
0
1
9
1
8
1
7
1
6
1
50
Reserved Don’t Care NODE ID
msb−p193−89
1000
INTR COMMAND IPL 14
IPL 15
IPL 16
1PL 17
INTERRUPT DESTINATION
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