User`s guide

The XMI
the bit is one, then that byte is written. For hexword-length Write Mask
transactions, the responder ignores the mask and writes all 32 bytes,
unless there is a matching entry in the deferred queue. Then only bytes
that were not updated by the deferred write are updated.
The MS65A memory module is quadword organized, and therefore all
writes that write less than an aligned quadword for each write data cycle
result in the generation of a read/modify/write operation in the memory.
Write Mask transactions in XMI memory space are masked. Write Mask
transactions in I/O space are node-implementation specific. Longword-
length transactions are used in I/O space; quadword- and octaword-length
transactions are only used in memory space.
All controllers that perform hexword Write Mask transactions also
implement a mode where all functions are accomplished without using
either hexword Write Mask or hexword Unlock Write Mask transactions.
The Enable Hexword Write (EHWW) bit in XBER enables the controller’s
use of hexword writes.
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