User`s guide

The XMI
Table 2–13 Memory Space Transactions
Command Length
Used
By
Command Cycle
Acknowledg-
ments
Request
Type
Flow
Control Possible Responses
READ HW, OW,
QW
CPU,
I/O
ACK or NO ACK
1
Cdr SUP GRD x , CRD x ,
2
RER
3
IREAD QW I/O
4
ACK or NO ACK
1
Cdr SUP GRD x , CRD x ,
2
LOC,
1
RER
3
OREAD HW CPU ACK or NO ACK
1
Cdr SUP GRD x , CRD x ,
2
LOC,
1
RER
3
WMASK HW, OW,
QW
CPU,
I/O
4
ACK or NO ACK
1
Cdr SUP
UWMASK HW, OW,
QW
CPU,
I/O
4
ACK or NO ACK
1
Cdr SUP
DWMASK HW CPU ACK or NO ACK
1
Cdr,
Res
5
SUP
6
TBDATA HW CPU ACK or NO ACK
1
Cdr,
Res
5
SUP
6
1
Reattempt transaction until timeout.
2
Done—Set CRD bit and interrupt, if enabled.
3
Done—Set RER bit and interrupt, if enabled.
4
CPUs use this transaction while the cache is disabled.
5
Responder request is used to perform writebacks if XMI SUP L is asserted.
6
Effectively uses NO ACK flow control if the CPUs are writing back using the responder request level while XMI
SUP L is asserted.
Table 2–14 I/O Space Transactions
Command Length
Used
By
Command Cycle
Acknowledg-
ments
Request
Type
Flow
Control Possible Responses
READ LW CPU,
I/O
ACK or NO ACK
1
Cdr NO ACK
2
GRD x , CRD x ,
3
RER
4
IREAD LW CPU,
I/O
ACK or NO ACK
1
Cdr NO ACK
2
GRD x , CRD x ,
3
LOC,
1
RER
4
WMASK LW CPU,
I/O
ACK or NO ACK
1
Cdr NO ACK
2
UWMASK LW CPU,
I/O
ACK or NO ACK
1
Cdr NO ACK
2
1
Reattempt transaction until timeout.
2
Memory nodes use XMI SUP L to control the flow of accesses to its I/O space.
3
Done—Set CRD bit and interrupt, if enabled.
4
Done—Set RER bit and interrupt, if enabled.
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