User`s guide

Contents
CHAPTER 3 DWMBB ADAPTER 3–1
3.1 DWMBB OVERVIEW 3–2
3.2 ADDRESS TRANSLATION 3–4
3.2.1 DWMBA Compatibility Mode 3–8
3.2.1.1 DWMBA Compatibility Mode DMA Write Transaction • 3–9
3.2.1.2 DWMBA Compatibility Mode DMA Read Transaction • 3–9
3.2.2 40-Bit VAX Address Translation 3–10
3.2.3 40-Bit Address Translation (4-Kbyte Page Size) 3–11
3.2.4 40-Bit Address Translation (8-Kbyte Page Size) 3–13
3.2.5 DMA Write Transactions—Extended Address Modes 3–15
3.2.6 DMA Read Transactions—Extended Address Modes 3–15
3.3 I/O TRANSACTIONS 3–16
3.3.1 I/O References to DWMBB/A Module Registers 3–16
3.3.2 I/O References to the PMRs 3–17
3.3.3 I/O References to DWMBB/B Module Registers or to VAXBI
Registers 3–17
3.4 INTERRUPTS 3–18
3.4.1 DWMBB-Detected Error Interrupt Vectors 3–21
3.4.2 VAXBI Node Vector 3–21
3.4.3 Interprocessor Interrupts 3–23
3.4.4 Interrupt Transactions 3–23
3.4.4.1 DWMBB Adapter-Generated Interrupts • 3–23
3.4.4.2 VAXBI-Generated Interrupts • 3–23
3.4.4.3 BIIC-Generated VAXBI Interrupts • 3–23
3.4.4.4 Interprocessor-Generated VAXBI Interrupts • 3–24
3.4.4.5 Passive Release of VAXBI Interrupts • 3–24
3.4.5 IDENT Transactions 3–24
3.4.6 Return Vector Disable Option 3–24
3.4.7 IVINTR Transactions 3–25
3.5 VAXBI WRAPPED READ TRANSACTIONS 3–26
3.6 LOCKOUT MODES 3–28
3.6.1 No Assertion and No Response to XMI Lockout Mode 3–29
3.6.2 Respond to XMI Lockout Mode 3–29
3.6.3 Assert XMI Lockout Mode 3–29
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