User`s guide

The XMI
The XMI protocol architecturally supports up to 16 XMI nodes. However,
the VAX 6000 implementation supports 14 nodes. Each node on the XMI
bus has a hexadecimal identification number (1 through E) called the node
ID, which is provided by the node’s hardwired XMI NODE ID<3:0> H
lines. The physical slot number equals the node ID. Slot 1 is the rightmost
slot in the XMI card cage when viewed from the front of the cabinet.
Any or all nodes may desire the use of the XMI at any given time.
Arbitration cycles occur in parallel with data transfer cycles by using
a set of lines dedicated to arbitration. The XMI CMD REQ L line, the
XMI RES REQ L line, and the XMI GRANT L line go between the central
arbiter and each node. The XMI CMD REQ L line is used by nodes to
initiate XMI transactions (to act as a commander), while the XMI RES
REQ L line is used to return data to a commander (to act as a responder).
The XMI arbiter maintains two independent round-robin queues, one for
each of the request types. The responder requests have a higher priority
than commander requests.
During any given cycle, all nodes have the opportunity to request the bus.
The arbiter receives all the requests, decides which node will be granted
the bus, and uses that node’s XMI GRANT L line to tell the node that it
has been selected. In the next cycle, the selected node begins its transfer.
The XMI has two additional arbitration control signals, XMI HOLD L and
XMI SUP L. The assertion of XMI SUP L suppresses all commander
requests but allows responder requests to continue to be serviced.
Assertion of XMI HOLD L guarantees that the current XMI transmitter
will be granted ownership of the bus in the next cycle, independent of
the value of any other outstanding requests. The XMI HOLD L signal
is used for multicycle transfers, allowing the current transmitter to keep
ownership of the bus for consecutive cycles. In general, XMI HOLD L
is used to transfer contiguous quadwords during octaword and hexword
transfers.
A node can temporarily block the start of additional XMI transactions by
asserting the XMI SUP L signal should it have difficulties in keeping up
with bus traffic. Examples of the assertion of XMI SUP L are a memory
command queue becoming full or a CPU invalidate queue backing up
during cache invalidate operations due to XMI writes.
The XMI arbitration scheme consists of three priority classes:
• Hold, which has the highest priority and guarantees that the current
transmitter will be granted the bus in the next cycle.
• Responder requests, the next highest priority.
• Commander requests, the lowest priority.
Within the responder and commander classes, priority is distributed in a
round-robin manner.
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