User`s guide

The XMI
2.1.6 XMI Interrupt Transactions
The XMI supports three types of interrupt transactions, listed in
Table 2–3.
Table 2–3 XMI Interrupt Transactions
Type Mnemonic
Interrupt Request INTR
Identify (Interrupt Acknowledge) IDENT
Implied Vector Interrupt IVINTR
The INTR and IDENT transactions implement device interrupts. An I/O
node issues an INTR transaction to a processor to interrupt the processor
at a specified interrupt priority level (IPL). The processor responds to
the INTR by issuing an IDENT transaction to the interrupting I/O node,
soliciting an interrupt vector.
An INTR transaction can be broadcast to multiple processor nodes. The
first processor to respond with IDENT receives the interrupt vector. All
other processors, upon seeing the IDENT, cease their interrupt-pending
condition.
The IVINTR transaction implements single-cycle interrupt transactions
where the interrupt priority and the interrupt vector value are implied
by bits in the interrupt type field. The IVINTR transaction implements
VAX interprocessor interrupts (IPL = 16 (hex), vector = 80 (hex)) and write
error interrupts (IPL = 1D (hex), vector = 60 (hex)). Since the value of
the interrupt vector is indicated by the value of the IPL field, IVINTR
transactions do not require a corresponding interrupt acknowledge cycle.
See Section 2.5.9 and Section 2.5.10 for more information on interrupt
transactions.
2–10