User`s guide

The XMI
The XMI consists of the electrical environment of the XMI bus, the protocol
observed by a node on the bus, the backplane, and the logic used to
implement the protocol.
The XMI is a limited length, pended, and synchronous bus with centralized
arbitration. Several transactions can be in progress at a given time,
allowing highly efficient use of the bus bandwidth. Arbitration and data
transfers can occur simultaneously. When the XMI is used as a system
bus, the XMI can support either a writethrough or a writeback cacheing
scheme. The protocols for the two cacheing schemes are different and
therefore cannot be mixed. For certain applications the use of writeback
caches decreases XMI bus write traffic thus increasing the performance of
the system. The bus supports:
• Quadword-, octaword-, and hexword-length reads and writes to
memory
• Longword-length read and write operations to I/O space
The longword operations implement byte and word modes required by
certain I/O devices. The XMI has a 64 ns bus cycle. The XMI has a
bandwidth of 125 Mbytes per second; however, the usable bandwidth
depends on transaction length (see Table 2–1).
Table 2–1 Usable XMI Bandwidth
Operation Bandwidth (Mbytes/second)
Longword (4 bytes) Read 31.25
Quadword (8 bytes) Read 62.50
Octaword (16 bytes) Read 83.30
Hexword (32 bytes) Read 100.00
Longword Write 31.25
Quadword Write 62.50
Octaword Write 83.30
Hexword Write 100.00
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