User`s guide

Index
Write Data NO ACK bit • 2–62, 3–48, 3–124
Write error interrupt • 2–80
Write Error Interrupt bit • 2–60, 3–47
Write Error IVINTR • 2–80
Write Mask transaction • 2–38
Write Sequence Error bit • 2–61, 3–48, 3–124
Write transactions • 2–50 to 2–51
WSE bit
See Write Sequence Error bit
X
XBAD bit
See XMI BAD bit
XBADD bit
See XMI BAD Drive bit
XBEER register
See Bus Error Extension Register
XBER register
See Bus Error Register
XBI INT PEND bit
See DWMBB Interrupt-Pending Status bit
XBI Power-Up LED bit
XCI AC LO L signal • 2–53 to 2–55
XCI DC LO L signal • 2–53 to 2–55
XCR register
See XMI Control Register
XDEV register
See Device Register
XFADR register
See Failing Address Register
XFAER register
See Failing Address Extension Register
XGPR register
See XMI General Purpose Register
XMI-1 platform • 1–2
XMI-2 platform • 1–2
XMI AC LO L signal • 2–53 to 2–55, 3–130
XMI BAD bit • 2–60, 3–47
XMI BAD Drive bit • 2–71
XMI BAD L signal • 2–53 to 2–55, 3–98
XMI card cage • 1–8
XMI CMD REQ L signal • 2–11, 2–21
XMI CNF signal • 2–76
XMI Control Register • 2–70
XMI Corner • 2–4
XMI D<63:0> L signals • 2–76
XMI DC LO L signal • 2–53 to 2–55, 3–130
XMI F<3:0> L signals • 2–76
XMI Failing Address Extension Register • 3–92
XMI Failing Address Register • 3–53
XMI General Purpose Register • 2–68
XMI GRANT[n] L signals • 2–11, 2–21
XMI HOLD L signal • 2–21
XMI ID<5:0> L signals • 2–76
XMI initialization • 2–53 to 2–55
XMI Lockout Assert bit • 3–131
XMI Lockout Limit field • 3–131
XMI LOCKOUT L signal • 3–28, 3–147
XMI Lockout Response bit • 3–131
XMI NODE ID<3:0> H signals • 2–21
XMI P<2:0> L signals • 2–76
XMI RESET L signal • 2–53 to 2–55
XMI Reset Timing Control Logic • 4–3
XMI RESPONDER REQUEST L signal • 2–21, 3–33
XMI RES REQ L signal • 2–11
XMI SUP L signal • 2–21, 3–33
XMI Timeout bit • 3–131
XMI Timeout Limit field • 3–131
XMIT LOCKOUT STATUS bit
See Transmit Lockout Status bit
XMI Trigger bit • 2–60, 3–47
XTC • 2–54, 4–3
XTC power sequencer
See XTC
Index–9