User`s guide

Index
Force Bad IBUS Receiver Parity bit • 3–79
Force Bad IBUS Transmit Parity bit • 3–79, 3–145
Force BCI Bad Parity bit • 3–110, 3–146
Force BIIC Loopback Mode bit • 3–110, 3–135
Force Data NO ACK bit • 3–75, 3–148
Force DMA-A Buffer Busy bit • 3–79, 3–140, 3–141,
3–142
FORCE DMA-A BUSY bit
See Force DMA-A Buffer Busy bit
Force DMA-B Buffer Busy bit • 3–79, 3–140, 3–141,
3–142
FORCE DMA-B BUSY bit
See Force DMA-B Buffer Busy bit
Force ECC Error bit • 3–77, 3–146
Force Illegal Command bit • 3–76, 3–148
Force Octaword Transfers bit • 3–78, 3–139, 3–141
FORCE OCTAWORD XFER bit
See Force Octaword Transfers bit
Force Tlockout bit • 3–147
Force Transmit lockout bit • 3–77
FOR ILL CMD bit
See Force Illegal Command bit
G
Good Read Data bit • 3–30
H
H405 AC power controller • 4–2
H7206-B power and logic unit • 4–2
H7236-A battery backup unit • 4–6
operation • 4–6
I
I/O connections • 1–11
I/O space • 2–13, 2–14
I/O transactions • 3–16 to 3–17
I/O Write Failure bit • 3–60, 3–121, 3–122, 3–127,
3–128, 3–130, 3–135
IBUS • 1–10, 3–2
IBUS DMA-A C/A Parity Error bit • 3–62, 3–119,
3–120, 3–123
IBUS DMA-A CA PE bit
See IBUS DMA-A C/A Parity Error bit
IBUS DMA-A Data Parity Error bit • 3–61, 3–119
IBUS DMA-A DATA PE bit
See IBUS DMA-A Data Parity Error bit
IBUS DMA-B C/A Parity Error bit • 3–62, 3–119,
3–120, 3–123
IBUS DMA-B CA PE bit
See IBUS DMA-B C/A Parity Error bit
IBUS DMA-B Data Parity Error bit • 3–62, 3–119
IBUS DMA-B DATA PE bit
See IBUS DMA-B Data Parity Error bit
IBUS I/O RD PE bit
See IBUS I/O Read Data Parity Error bit
IBUS I/O Read Data Parity Error bit • 3–63, 3–120,
3–135
IBUS Parity Error bit • 3–120
IBUS Parity Error Interrupt Mask bit • 3–99
IBUS PE INTR MASK
See IBUS Parity Error Interrupt Mask bit
IDENT ERR bit
See IDENT Error bit
IDENT Error bit • 3–103
Identify transactions
See IDENT
IDENT transactions • 2–43
IL I/O CMD bit
See Illegal CPU Command bit
Illegal CPU Command bit • 3–102, 3–148
Illegal I/O Command bit • 3–122
Implied Vector Interrupt Destination/Diagnostic
Register • 3–72
Implied vector interrupts • 3–114
Implied Vector Interrupt transaction
See IVINTR
Inconsistent Parity Error bit • 2–61, 3–48, 3–124
Inconsistent parity errors • 2–76
InfoServer 100 • 1–9
Initialization • 2–53 to 2–55, 3–130 to 3–132
INTERLOCK
n signal • 4–6
Interlock Read transactions • 2–35
Internal Error bit • 3–60, 3–123, 3–128, 3–135
Interrupt Destination field • 3–105
Interrupt Destination Register • 3–105
Interrupt Mask Register • 3–64
Interrupt on BCI AC LO bit • 3–70
Interrupt on Command NO ACK bit • 3–68
Interrupt on Correctable ECC Error bit • 3–69, 3–117,
3–118
Interrupt on Corrected Confirmation bit • 3–66
Interrupt on Corrected Read Data bit • 3–67
Interrupt on DMA-A Data Parity Error bit • 3–70
Interrupt on DMA-B Data Parity Error bit • 3–70
Index–4