User`s guide

DWMBB Adapter
3.14.8 Diagnostic Read/Write Registers
The DWMBB has two registers that act as temporary storage registers
for diagnostics routines. They are readable/writable and can be used
in loopback mode to verify the integrity of the main data paths. These
registers follow:
• AIVINTR<31:0> – Used to verify the IBUS
• BIDR<31:0> – Used to verify the IBUS and VAXBI
3.14.9 Miscellaneous Diagnostic Bits
Three bits aid in testing the Error Summary, RIDNAK, WDNAK, NRR,
and Illegal CPU Command bits in XBER and BESR. The bits are as
follows:
• Error Summary Test (ADG1<28>) – Allows diagnostics to test Error
Summary (XBER<31>). When set, Error Summary Test disables
Self-Test Fail (XBER<10>) from setting Error Summary.
• Force Data NO ACK (ADG1<27>) – Allows diagnostics to test
RIDNAK (XBER<21>) and NRR (XBER<18>). When set, Force Data
NO ACK forces the following:
– The DWMBB to receive a NO ACK instead of an ACK for DMA
write data and I/O read data cycles
– The DWMBB to time out waiting for return of DMA read data
• Force Illegal Command (ADG1<26>) – Allows diagnostics to test
Illegal CPU Command (BESR<3>). When set, this bit forces an illegal
(reserved) function code of zero to be issued on the IBUS in a C/A cycle
that the DWMBB accepts from the XMI and sends to the DWMBB/B
module.
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