User`s guide

DWMBB Adapter
Figure 3–17 (Cont.) Testing the DMA Transmit and Receive Registers
5. Do a DMA loopback write/read pair with I/O Address Bit<2> set to zero:
6. Do a DMA loopback write/read pair with I/O Address Bit<2> set to one:
7. Do an I/O write to ADG1 to deassert DWMBB/A Flip FADDR<1> and
8. Repeat steps 2 through 6. Use different address patterns but
I/O write − I/O address = XX XXDE FED0#16
− I/O data = 1111 1111#16
LOCATIONS TESTED:
TRANSMIT RECEIVE
DMAA C/A <41:0>
DMAA LW2 <31:0>
DMAA C/A <41:0>
DMAA LW3 <31:0>
1111
1111
03E0#16 when repeating step 4, to
msb−p099−89
I/O read − Same address as I/O write
DMA LW2
EEEE EEEE#16
1234#16
LOCATIONS TESTED:
00 1111
1234
I/O write − I/O address = XX XX56
00DE FED0
=
0000 01A0#16
Force Octaword Transfers and to set Force DMAA Buffer Busy:
TRANSMIT RECEIVE
I/O read
1111
DMA LW3
maintain the needed status of I/O Address Bit<2> for each step.
00 EEEE EEEE
I/O write − I/O data
− I/O data
=
Use I/O write data = 0000
− Same address as I/O write
keep Force DMAB Buffer Busy set while also setting DWMBA/A
Flip FADDR<1> and Force Octaword Transfers.
0056
EEEE EEEE
3–144