User`s guide

DWMBB Adapter
Figure 3–16 DWMBB/A Module Receive Registers
ADDRESS BUFFERS
IM FADDR<3:0> = 0
IM FADDR<3:0> = 1
IM FADDR<3:0> = 4
IM FADDR<3:0> = 5
IM FADDR<3:0> = 6
IM FADDR<3:0> = 7
I/O C/A BUFFER
msb−p097−89
I/O DATA BUFFER
DMA−A LONGWORD DATA 1
DMA−A LONGWORD DATA 2
DMA−A LONGWORD DATA 3
DMA−A LONGWORD DATA 4
Table 3–19 Diagnostic Bits That Test DMA Buffers in Loopback Mode
Diagnostic Bit Location Description
DWMBB/A Loopback
Enable
ADG1<7> When set, places the DWMBB/A module in DWMBB/A module
loopback mode and disables the IBUS drivers. This bit, when set,
results in an illegal address error unless DWMBB/A Flip Address
Bit<29> is also set. See below.
DWMBB/A Flip Address
Bit<29>
ADG1<8> When set, converts I/O transactions targeted for the DWMBB/B
module into DWMBB/A module loopback DMA transactions targeted
for XMI memory. This bit must be set with DWMBB/A Loopback
Enable so the transaction looks like a DMA transaction originating
from the VAXBI, preventing an illegal address error.
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