User`s guide

DWMBB Adapter
While in DWMBB/A module loopback mode, the IBUS drivers are turned
off and I/O commands from the XMI are looped back to the IBUS DMA
input command/address latches in the DWMBB/A module gate array. If a
parity error or PFN error is found during the C/A cycle, the appropriate
bits set in AESR.
I/O write data does not loop back through the gate array transceivers but
is transferred internally in the gate array, taking the same path that the
PMR write data takes. Parity is checked on this internal transfer and, if
a parity error is found, Internal Error (AESR<5>) and I/O Write Failure
(AESR<3>) set.
When I/O read data is returned, it is looped back through the gate array
transceivers. If a parity error occurs on the read data cycle, IBUS I/O
Read Data Parity Error (AESR<0>) sets.
Once the looped back C/A cycle is latched off the IBUS, the address
is decoded and, if DWMBB/A Flip Address Bit<29> was not set with
DWMBB/A Loopback Enable, an illegal address error occurs because the
address is pointing to I/O space instead of XMI memory space. Invalid
VAXBI Address (AESR<8>) sets to verify the logic that detects illegal
VAXBI addresses.
During normal operation the DWMBB/A module clears bits <28:25>
of the I/O command/address when transferring an I/O C/A cycle to the
DWMBB/B module as the DWMBB has only 32 Mbytes of addressable I/O
adapter space. These bits should always be zero during DWMBB/A module
loopback mode because the C/A cycle targeted for the DWMBB/B module
is looped back.
DWMBB/A loopback mode prevents normal DMA transactions and
interrupts. However, Interrupt Sent Status (ADG1<1>) indicates that the
interrupt flag would set if enabled. Examining this bit while forcing error
conditions allows diagnostic software to verify the DWMBB/A module’s
error logic without generating interrupts.
3.14.1.2 BIIC Loopback
When the BIIC is in loopback mode, the main data path includes the
DWMBB/A module, the IBUS, and the DWMBB/B module, but not the
VAXBI. The mode is entered by setting Force BIIC Loopback Mode
(BDCR1<3>). In this mode, longword read and write transactions
targeting the BIIC registers are made without the use of the VAXBI
data lines because the drivers to the VAXBI are turned off. The BIIC
registers are located in the first 256 bytes of the DWMBB/B module’s
VAXBI nodespace.
BIIC loopback mode allows a node to access its nodespace registers without
reference to its node ID because D<29:13> of the address, which select the
node address space, are ignored by the BIIC’s address selection logic except
for parity checking. The BIIC completes the transfer as though D<29:13>
were set to 10 0000 0000 000n nnn, where n nnn is the appropriate node
ID of this node. Loopback mode can then be used during power-up, when
the node’s ID is unknown.
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