User`s guide

DWMBB Adapter
3.12.8 Miscellaneous Errors
These errors originate on the control logic and during DWMBB operation
but do not pertain to the data paths.
3.12.8.1 Impending Power Fail
The BCI AC LO L signal asserts to warn of an impending power fail on the
VAXBI. This sets BCI AC LO (AESR<5>), causing the DWMBB to generate
an IVINTR on the XMI if Enable IVINTR Transactions (AIMR<31>) is set.
The DWMBB completes any current transaction in progress and stops
processing further transactions.
3.12.8.2 Internal Errors
Internal Error (AESR<7>) sets if the DWMBB/A module’s gate array
control logic reaches an illogical state. When Internal Error sets, the
DWMBB generates an IVINTR on the XMI if Enable IVINTR Transactions
(AIMR<31>) is set, aborts any transaction in progress, and returns to an
idle state to receive further requests.
The following conditions set Internal Error:
• A state machine in the DWMBB/A module’s gate array reaches an
illogical state.
• A parity error is detected internal to the gate array on the transfer of
PMR write data for a PMR write request. This means that the PMR
location’s data is corrupt and I/O Write Fail (AESR<6>) also sets.
• A parity error is detected on the transfer of write data for a loopback
write command. This also causes the loopback write transaction to
abort and I/O Write Fail (AESR<6>) to set.
• A parity error is detected on the return of DMA read data that is
looped back as CPU read data during loopback mode. This also causes
the loopback read transaction to abort.
3.12.8.3 PMR Initialization Inhibit Error
PMR control logic requires an 8.4-ms period for the PMRs to initialize
after a power-up or an XMI node reset. During this time, PMR Ready
(ACSR<29>) clears to prevent access of the PMRs from the XMI and the
VAXBI, disabling address translation. All I/O references to the PMRs are
NO ACKed while PMR Ready is clear.
System software must ensure that hardware has set PMR Ready and
that the PMRs are properly set up before address translation is enabled.
Otherwise, Invalid PFN Entry (AESR<11>) and/or either Uncorrectable
PMR ECC Error (AESR<12>) or Correctable PMR ECC Error (AESR<13>)
are set if address translation is enabled and a DMA request is received
from the DWMBB/B module.
3–128