User`s guide

DWMBB Adapter
3.12.6.5 Parity Errors on the XMI
The DWMBB sets PE whenever it detects a parity error on an XMI cycle
and sets IPE whenever it detects a parity error on an XMI cycle that is
ACKed. If a parity error is detected on the XMI during an I/O write C/A,
I/O read C/A, I/O write data, or an IDENT cycle, the transaction is NO
ACKed and PE set. An INTR is generated if Interrupt on Parity Error
(AIMR<23>) is set.
If a parity error is detected on returning DMA quadword read data, the
read is NO ACKed and the DMA quadword read eventually fails by timing
out. TTO, NRR, and PE set and an INTR is generated if the appropriate
AIMR bits are enabled.
If a parity error is detected on the first quadword of a DMA octaword
read request and the second read data quadword has no errors, the first
quadword is NO ACKed, the second quadword is ACKed, RSE and PE set,
and the read fails. An INTR is generated if the appropriate AIMR bits are
enabled.
If a parity error is detected on the second quadword, or both quadwords, of
a DMA octaword read request, the quadwords with parity errors are NO
ACKed and the DMA transaction times out. TTO, NRR, and PE set and
an INTR is generated if the appropriate AIMR bits are enabled.
3.12.6.6 I/O Read Data and IDENT Vector Errors on the XMI
The DWMBB is an XMI responder during data cycles of I/O read and
IDENT transactions. If an error is detected at the XMI commander node
during a read data cycle of either of these transactions, the commander
NO ACKs the data, setting RIDNAK and causing the address of the I/O
transaction to be logged in AREAR<29:0>. An INTR is generated if INTR
RIDNAK (AIMR<21>) is set.
3.12.6.7 I/O Write Data Error on the XMI
The DWMBB is an XMI responder during data cycles of I/O write
transactions. If an error is detected during a write data cycle, the
following happen:
• WSE sets for a write sequence error or PE sets for a parity error.
• The write data cycle is NO ACKed by the DWMBB.
• The I/O address is logged in AREAR<29:0> if WSE is set.
• An INTR is generated if the interrupt enable bits for either of these
errors are set in AIMR.
3.12.6.8 LOC Response on DMA Read Data
When the DWMBB receives a LOC response in reply to either an
Interlock Read or a Read transaction, it returns a retry to the VAXBI.
The transaction is assumed to be successful. No error bits are set, and no
interrupts are generated.
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