User`s guide

DWMBB Adapter
3.12.6.1 DMA Write C/A XMI Error
The DWMBB operates as an XMI commander during a DMA write
transaction. It starts a retry counter as it begins executing the DMA
write by arbitrating for the XMI. Errors encountered while transmitting
the DMA write cause retries until it completes successfully or the retry
counter times out, which causes the DMA write to be considered a failure.
If an error is detected during the C/A cycle of the DMA write transaction,
TTO and CNAK set as appropriate for that error. An IVINTR transaction
is generated if Enable IVINTR Transactions (AIMR<31>) is set. An INTR
transaction is generated if the corresponding interrupt enable bits are set
in AIMR.
3.12.6.2 DMA Read C/A XMI Error
The DWMBB operates as an XMI commander during a DMA read
transaction. It starts a retry counter as it begins executing the DMA
read by arbitrating for the XMI. Errors encountered while transmitting
the DMA read cause retries until it completes successfully or the retry
counter times out, which causes the DMA read to be considered a failure.
If an error is detected during the C/A cycle of the DMA read transaction,
TTO and CNAK set as appropriate for that error. The DWMBB/A module
informs the DWMBB/B module that the DMA read failed, and the VAXBI
node is NO ACKed. An INTR transaction is generated if the corresponding
interrupt enable bits are set in AIMR.
3.12.6.3 DMA Write Data XMI Error
The DWMBB operates as an XMI commander during a DMA write
transaction. It starts a retry counter as it begins executing the DMA
write by arbitrating for the XMI. Errors encountered while transmitting
the DMA write data cause retries until it completes successfully or the
retry counter times out, which causes the DMA write to be considered a
failure.
If an error is detected during a data cycle of the DMA write transaction,
TTO and WDNAK set as appropriate for that error. An IVINTR
transaction is generated if Enable IVINTR Transactions (AIMR<31>)
is set. An INTR transaction is generated if the corresponding interrupt
enable bits are set in AIMR.
3.12.6.4 DMA Read Data XMI Error
The DWMBB operates as an XMI commander during a DMA read
transaction. It starts a retry counter as it begins executing the DMA
read by arbitrating for the XMI.
If an error is detected while receiving a data cycle for the DMA read
transaction, PE, NRR, RER, RSE, and TTO set as appropriate for that
error. The DWMBB/A module does not retry the DMA read transaction
when errors are detected in the read data cycle. The DMA read is
considered a failure if the read data is in error or is not returned within
the timeout window. The DWMBB/A module informs the DWMBB/B
module that the DMA read failed, and the VAXBI node is NO ACKed. An
INTR transaction is generated if the corresponding interrupt enable bits
are set in AIMR.
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