User`s guide

DWMBB Adapter
3.12.5.11 Undecodable DMA C/A with no IBUS Parity Error Detected
If all the following occur,
• A DMA C/A cycle is loaded into the DWMBB/A module.
• The command field is undecodable.
• No parity error is detected.
• The DWMBB/B module does not nullify the DMA transaction.
The DWMBB/A module sets Internal Error (AESR<7>), causing an
IVINTR to be issued, if IVINTRs are enabled, and the DMA address is
logged in ABEAR<29:0>.
If the DWMBB/B module nullifies the transaction, the appropriate error
bits are set in the DWMBB/B module’s control and status registers and
the DWMBB/B module generates an INTR, if INTRs are enabled.
3.12.5.12 Undecodable DMA C/A with an IBUS Parity Error Detected
If all the following occur,
• A DMA C/A cycle is loaded into the DWMBB/A module.
• The command field is undecodable.
• A parity error is detected.
• The DWMBB/B module does not nullify the transaction.
The DWMBB/A module sets either IBUS DMA-A C/A Parity Error
(AESR<3>) or IBUS DMA-B C/A Parity Error (AESR<1>), as appropriate,
logs the VAXBI address in ABEAR<29:0>, and issues an IVINTR, if
IVINTRs are enabled.
If the DWMBB/B module nullifies the transaction, the appropriate error
bits are set in the DWMBB/B module’s control and status registers and
the DWMBB/B module generates an INTR, if INTRs are enabled.
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