User`s guide

DWMBB Adapter
• Generates an IVINTR if Enable IVINTR Transactions (AIMR<31>) is
set
3.12.5.6 I/O Write C/A IBUS Parity Error
If an IBUS parity error is detected by the DWMBB/B module during an
I/O write C/A cycle, the DWMBB/B module does the following:
• Sets DWMBB/B-Detected IBUS Parity Error (BESR<0>)
• Sets Command/Address Fetch Failed (BESR<6>)
• Sets Master Sequencer Transaction Failed (BESR<4>)
• Aborts the transaction
• Informs the DWMBB/A module that the I/O transaction failed
The DWMBB/A module then does the following:
• Sets I/O Write Failure (AESR<6>)
• Logs the address of the I/O command in AREAR<29:0>
• Generates an IVINTR if Enable IVINTR Transactions (AIMR<31>) is
set
3.12.5.7 I/O Write Data IBUS Parity Error
If an IBUS parity error is detected on I/O write data during an I/O write
data cycle by the DWMBB/B module, the DWMBB/B module does the
following:
• Sets DWMBB/B-Detected IBUS Parity Error (BESR<0>)
• Sets Master Sequencer Transaction Failed (BESR<4>)
• Aborts the transaction
• Informs the DWMBB/A module that the I/O transaction failed
The DWMBB/A module then does the following:
• Sets I/O Write Failure (AESR<6>)
• Logs the address of the I/O command in AREAR<29:0>
• Generates an IVINTR if Enable IVINTR Transactions (AIMR<31>) is
set
3.12.5.8 I/O Read C/A IBUS Parity Error
If an IBUS parity error is detected by the DWMBB/B module during an
I/O read C/A cycle, the DWMBB/B module does the following:
• Sets DWMBB/B-Detected IBUS Parity Error (BESR<0>)
• Sets Command/Address Fetch Failed (BESR<6>)
• Sets Master Sequencer Transaction Failed (BESR<4>)
• Aborts the transaction
• Informs the DWMBB/A module that the I/O transaction failed
The DWMBB/A module then returns an RER to the requesting XMI node.
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