User`s guide

DWMBB Adapter
• Generates an INTR if either INTR DMA-A Data Parity Error
(AIMR<4>) or INTR DMA-B Data Parity Error (AIMR<2>), as
appropriate, is set
3.12.5.3 DMA Read C/A IBUS Parity Error
If an IBUS parity error is detected on the Command/Address during
a DMA read cycle and the DWMBB/B module does not nullify the
transaction, the DWMBB/A module does the following:
• Sets either IBUS DMA-A C/A Parity Error (AESR<3>) or IBUS DMA-B
C/A Parity Error (AESR<1>), as appropriate
• Logs the VAXBI address of the DMA transaction in ABEAR<29:0>
• Aborts the transaction
• Returns a NO ACK to the VAXBI
• Generates an INTR if either INTR DMA-A C/A Parity Error
(AIMR<3>) or INTR DMA-B C/A Parity Error (AIMR<1>), as
appropriate, is set
• Generates an IVINTR if Enable IVINTR Transactions (AIMR<31>) is
set
3.12.5.4 I/O Read Data or IDENT Vector IBUS Parity Error
If an IBUS parity error is detected when I/O read data or an IDENT vector
is transferred over the IBUS and the DWMBB/B module does not nullify
the transaction, the DWMBB/A module does the following:
• Sets IBUS I/O Read Data Parity Error (AESR<0>)
• Logs the address of the I/O command in AREAR<29:0>
• Returns an RER and the corrupted I/O read data, with good parity, on
the XMI for an I/O read data parity error
• Returns a GRD0 and the contents of the Return Vector Register
(ARVR) to the requesting XMI commander node for a parity error on
an IDENT vector, unless Return Vector Disable (ACSR<1>) is set
• Returns an RER to the requesting XMI commander node for a parity
error on an IDENT vector if Return Vector Disable (ACSR<1>) is set
• Generates an INTR if Interrupt on IBUS I/O Read Data Parity Error
(AIMR<0>) is set
3.12.5.5 DMA Read Data IBUS Parity Error
If an IBUS parity error is detected on the read data during a DMA read
cycle, the DWMBB/B module does the following:
• Sets DWMBB/B-Detected IBUS Parity Error (BESR<0>)
• Sets Slave Sequencer Transaction Failed (BESR<5>)
• Sets VAXBI Interlock Read Failed (BESR<2>) for DMA Interlock
Reads only
• Generates an INTR if Enable DWMBB Interrupts (BCSR<31>) is set
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