User`s guide

DWMBB Adapter
3.12.5 IBUS Parity Errors
The DWMBB detects IBUS parity errors on all cycles.
The DWMBB/A module detects IBUS parity errors on the following cycles:
• DMA write C/A or INTR C/A
• DMA write data
• DMA read C/A
• I/O read data or IDENT vector
The DWMBB/B module detects IBUS parity errors on the following cycles:
• DMA read data
• I/O write C/A
• I/O write data
• I/O read or IDENT C/A
3.12.5.1 DMA Write C/A or INTR C/A IBUS Parity Error
If an IBUS parity error is detected during a DMA write cycle or an INTR
C/A cycle and the DWMBB/B module does not nullify the transaction, the
DWMBB/A module does the following:
• Sets either IBUS DMA-A C/A Parity Error (AESR<3>) or IBUS DMA-B
C/A Parity Error (AESR<1>), as appropriate
• Logs the VAXBI address of the DMA transaction in ABEAR<29:0>
• Aborts the transaction
• Generates an IVINTR if Enable IVINTR Transactions (AIMR<31>) is
set
• Generates an INTR if either INTR DMA-A C/A Parity Error
(AIMR<3>) or INTR DMA-B C/A Parity Error (AIMR<1>), as
appropriate, is set
3.12.5.2 DMA Write Data IBUS Parity Error
If an IBUS parity error is detected on DMA write data during a DMA write
data cycle and the DWMBB/B module does not nullify the transaction, the
DWMBB/A module does the following:
• Sets either IBUS DMA-A Data Parity Error (AESR<4>) or IBUS
DMA-B Data Parity Error (AESR<2>), as appropriate
• Logs the VAXBI address of the DMA transaction in ABEAR<29:0>
• Aborts the transaction
• Generates an IVINTR if Enable IVINTR Transactions (AIMR<31>) is
set
3–119