User`s guide

DWMBB Adapter
3.12.4.1 Invalid VAXBI Address
An invalid VAXBI address error can occur at any time (while the DWMBB
is in DWMBA compatibility mode as well as in the address translation
modes).
The DWMBB/A module checks the appropriate VAXBI address bits (as
shown in Table 3–15) to determine the validity of the address during a
DMA read or write transaction. These address bits must be zero to be
valid. The following occurs:
• The DWMBB/A module:
– Sets Invalid VAXBI Address (AESR<8>)
– Aborts the DMA request
– Logs the invalid VAXBI address in ABEAR
– Generates an INTR if Interrupt on Invalid VAXBI Address
(AIMR<8>) is set
– Generates an IVINTR if the failed DMA transaction is a write and
Enable IVINTR Transactions (AIMR<31>) is set
Table 3–15 VAXBI Valid Address Check
Operating Mode
Address Bit(s)
(MBZ)
DWMBA compatibility (30-bit VAX address) VAXBI A<29>
40-bit VAX address translation VAXBI A<29:25>
40-bit address translation using 4-Kbyte pages VAXBI A<29:28>
40-bit address translation using 8-Kbyte pages VAXBI A<29>
3.12.4.2 Invalid PFN
The valid bit of the desired page frame number is checked during address
translation of the DMA command. If the valid bit is not set, meaning that
the PFN is not valid, then:
• The DWMBB/A module does the following if Invalid PFN (AESR<11>)
is set:
– Aborts the DMA request
– Logs the VAXBI address in ABEAR
– Generates an INTR if Interrupt on Invalid PFN (AIMR<11>) is
set
– Generates an IVINTR if the DMA transaction was a write and
Enable IVINTR Transactions (AIMR<31>) is set
3–116