User`s guide

DWMBB Adapter
3.12.3 Multiple Errors
When an error is detected, the registers listed in Table 3–14 are locked and
cannot be updated until the corresponding error bits have been cleared by
an XMI commander node. If another error occurs before the first error is
processed, a status bit is set to indicate the occurrence of multiple errors.
The multiple error flags are Multiple Errors (AESR<14>) and Multiple
CPU Errors (BESR<7>).
On power-up or node reset, the DWMBB defaults to generating only one
outstanding DWMBB interrupt at a time even though multiple error bits
may be set in its CSRs. Further INTRs are disabled until software clears
all error bits in the CSRs.
If Multiple Interrupt Enable (ACSR<3>) is set, the DWMBB issues an
INTR for every error detected, regardless of the number of previous errors
still logged in the CSRs.
3.12.4 Address Translation Mode Errors
When any address translation mode is enabled, the DWMBB checks for
the following:
• A valid VAXBI address
• No detected uncorrectable ECC errors on the page map register data
• A valid page frame number
If any of these error conditions are detected and the DWMBB/B module
does not nullify the DMA request on the IBUS, then the DWMBB/A
module aborts the DMA request, sets the appropriate error bit(s) in the
AESR, and logs the VAXBI address of the transaction that had the error.
If the error is an uncorrectable ECC error, the ECC syndrome is logged.
If the failed DMA transaction is a read, the DWMBB NO ACKs the
transaction and generates an INTR if interrupts are enabled. If the
failed DMA transaction is a write, the DWMBB generates an IVINTR
if the Enable IVINTR Transactions bit (AIMR<31>) is set. No status
information is transmitted back to the VAXBI node when a DMA write
fails, since writes are performed as disconnected writes.
A correctable ECC error detected during address translation is not a fatal
error. That is, the PMR data in error is corrected, and the transaction
completes. The DWMBB logs the error, the syndrome, and the VAXBI
address of the node generating the transaction. If the appropriate
interrupt enable bit is set in the AIMR, an INTR is also generated.
3–115