User`s guide

DWMBB Adapter
3.12.1 Error Interrupts
The DWMBB generates either Interrupts (INTRs) or Implied Vector
Interrupts (IVINTRs) in response to detected errors. An INTR is generated
at IPL 17 when INTRs are enabled. These INTRs are serviced before IPL
17 interrupts originating from the VAXBI.
The DWMBB/B module generates all INTRs. If the DWMBB/A module
detects an error condition requiring an INTR and the appropriate
interrupt enable bit is set, it asserts an interrupt error status flag on
the IBUS. When the DWMBB/B module sees the assertion of this flag, it
generates an INTR.
The DWMBB/A module generates IVINTRs, if IVINTRs are enabled,
when it detects errors that have the potential to lose data, such as write
transactions. These IVINTRs have the WRT ERROR INT bit set in the
Type field and the target node specified in the Destination field.
3.12.2 Error Command and Address Logging
Table 3–14 lists the registers that log the command and address of
transactions that fail and other error information needed for error
analysis. The registers are unlocked when associated error bits are
cleared.
Table 3–14 Registers That Log Failing Address and Command
Information
Register Field Logged Bits Locked
XFADR XMI Failing Address and Length <31:0>
XFAER XMI Failing Address Extension, Command, and Mask <31:0>
AREAR Responder Failing Address and Length <31:0>
AESR Responder Failing Node ID and Command <25:16>
ABEAR VAXBI Failing Address and Length <31:0>
BTIM VAXBI DMA Failing Address and Length <31:0>
3–114