User`s guide

DWMBB/B Module Registers
Timeout Address Register (BTIM)
Timeout Address Register (BTIM)
The Timeout Address Register is loaded each time a DMA command/address
is latched off the VAXBI. BTIM locks when (1) a VAXBI-to-XMI memory
Interlock Read fails, causing the VAXBI Interlock Read Failed bit (BESR<2>)
to set, or (2) a VAXBI-to-XMI memory read-type fails, causing the IBUS Parity
Error bit (BESR<0>) to be set by the DWMBB/B.
ADDRESS
XMI nodespace base address + 0000 004C
3
1
3
0
2
9 0
VAXBI DMA Failing Address
msb−p116−89
VAXBI DMA Failing Address Length
bits<31:30>
Name: VAXBI DMA Failing Address Length
Mnemonic: None
Type: RO
VAXBI DMA Failing Address length contains the length of the
received VAXBI-to-XMI transaction. The field is loaded on every
DMA command/address cycle received by the DWMBB/B module from
the IBUS. It locks if a failure is detected by the DWMBB/B module.
bits<29:0>
Name: VAXBI DMA Failing Address
Mnemonic: None
Type: RO
The VAXBI DMA Failing Address contains the longword physical
address of the received VAXBI-to-XMI transaction. If no errors are
detected, the register reads back the last VAXBI transaction. The
register logically locks upon error and unlocks when that error clears.
3–106