User`s guide

DWMBB/B Module Registers
Error Summary Register (BESR)
bit<0>
Name: DWMBB/B-Detected IBUS Parity Error
Mnemonic: B IBUS PE
Type: R/W1C, 0
DWMBB/B-Detected IBUS Parity Error sets if the DWMBB/B module
detects an IBUS parity error while fetching information from the
DWMBB/A module. The setting of DWMBB/B-Detected IBUS Parity
Error locks BESR<6:4> and, if the fetch was for DMA read return
data, the Timeout Address Register is also locked. When this bit is
cleared, BESR<6:4> and the Timeout Address Register are unlocked.
If IBUS Parity Error Interrupt Mask (BCSR<0>) is set, an error
interrupt is generated.
3–104