User`s guide

DWMBB/B Module Registers
Error Summary Register (BESR)
bit<5>
Name: Slave Sequencer Transaction Failed
Mnemonic: None
Type: RO, 0
Slave Sequencer Transaction Failed, when set with BESR<0>,
indicates that an IBUS parity error occurred while the slave sequencer
had control of the IBUS during a read data fetch from the DWMBB/A
module.
bit<4>
Name: Master Sequencer Transaction Failed
Mnemonic: None
Type: RO, 1
Master Sequencer Transaction Failed sets with BESR<0> to indicate
that an IBUS parity error occurred while the master sequencer had
control of the IBUS and a C/A or write data fetch is executing.
Master Sequencer Transaction Failed sets with every I/O transaction.
It is NOT VALID unless BESR<0> is also set. The transactions that
cause this error are I/O writes (C/A cycles only), I/O reads, and XMI
IDENTs.
bit<3>
Name: Illegal CPU Command
Mnemonic: None
Type: R/W1C, 0
Illegal CPU Command sets to indicate that an illegal CPU command
was decoded by the DWMBB/B module. The error results in the
master sequencer terminating the transaction and signaling the
DWMBB/A module that the transaction failed. The DWMBB/A
module then generates the appropriate error response on the XMI.
The transactions that cause this error are I/O writes (C/A cycles only),
I/O reads, and XMI IDENTs.
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