User`s guide

DWMBB/B Module Registers
Error Summary Register (BESR)
bit<12>
Name: DWMBB Interrupt-Pending Status
Mnemonic: XBI INT PEND
Type: RO, 0
DWMBB Interrupt-Pending Status, when set, indicates that a
DWMBB interrupt is pending.
bits<11:8>
Name: VAXBI Interrupt-Pending Status
Mnemonic: BR7–BR4
Type: RO, 0
The VAXBI Interrupt-Pending Status field sets to indicate that one or
more of the VAXBI interrupt-pending flip-flops is set. When asserted,
they indicate that a VAXBI-generated interrupt targeting the DWMBB
was successfully received and that an IDENT at the correct IPL on the
XMI has not yet been received. This field is a direct read of the VAXBI
interrupt-pending flip-flops, with BESR<11> corresponding to IPL<17>
and BESR<8> corresponding to IPL<14>.
bit<7>
Name: Multiple CPU Errors
Mnemonic: MULT CPU ERR
Type: R/W1C, 0
Multiple CPU Errors sets when BESR<3> and BESR<0> were set
during a previous fetch from the DWMBB/B module and a parity
error is detected on the current fetch. Multiple CPU Errors does not
set when both C/A and write data parity errors are detected. Such a
condition is considered the same transaction.
bit<6>
Name: Command/Address Fetch Failed
Mnemonic: CAFF
Type: RO, 0
When both Command/Address Fetch Failed and BESR<0> are set, the
DWMBB/B module detected an IBUS parity error on the C/A fetch
from the CPU C/A buffer.
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