User`s guide

DWMBB/B Module Registers
Error Summary Register (BESR)
Error Summary Register (BESR)
The BESR contains status bits for errors detected by the DWMBB/B module.
ADDRESS
XMI nodespace base address + 0000 0044
3
1
1
7
1
6
1
3
1
2
1
1 876543210
MUST BE ZERO
Interrupt Sent Status
DWMBB Interrupt−Pending Status
VAXBI Interrupt−Pending Status
Multiple CPU Errors
Command/Address Fetch Failed
Slave Sequencer Transaction Failed
Master Sequencer Transaction Failed
Illegal CPU Command
DWMBB/B−Detected IBUS Parity Error
msb−p114−89
VAXBI Interlock Read Failed
IDENT Error
bits<31:17>
Name: Reserved
Mnemonic: None
Type: RO, 0
Reserved; must be zero.
bits<16:13>
Name: Interrupt Sent Status
Mnemonic: Sent
Type: RO, 0
The Interrupt Sent Status field corresponds to the 4-bit interrupt
sent flops internal to the gate array, with BESR<16> corresponding
to IPL<17>, BESR<15> corresponding to IPL<16>, and so on. The
interrupt sent status flops and BSER<12:8> determine the current
interrupt-pending status.
3–100