User`s guide
DWMBB/A Module Registers
Control and Status Register (ACSR)
bit<1>
Name: Return Vector Disable
Mnemonic: RETURN VECTOR DIS
Type: R/W, 0
Return Vector Disable, when set, prevents the DWMBB from returning
the contents of the Return Vector Register in response to an unsolicited
or failed IDENT. Instead, the DWMBB issues a Read Error Response
to the XMI.
bit<0>
Name: Reserved
Mnemonic: None
Type: RO, 0
Reserved; must be zero.
3–90