User`s guide

DWMBB/A Module Registers
Control and Status Register (ACSR)
bit<5>
Name: VAXBI Window Space Enable
Mnemonic: BIWIN ENA
Type: R/W, 0
VAXBI Window Space Enable, when set, enables the VAXBI Window
Space field (AUTLR<13:0>), allowing software to reconfigure the
VAXBI I/O address space into any 32-Mbyte address of the 512-Mbyte
I/O address space.
bit<4>
Name: Responder Request Enable
Mnemonic: RES REQ ENA
Type: R/W, 0
Responder Request Enable, when set, causes the DWMBB to arbitrate
for the XMI as a commander using the XMI RESPONDER REQUEST
L signal instead of the XMI COMMANDER REQUEST L signal. If
the XMI SUP L signal is asserted when the DWMBB wins the XMI, it
aborts the transaction and retries again when the XMI SUP L signal
is deasserted, allowing the DWMBB a higher priority than other XMI
commander nodes.
bit<3>
Name: Multiple Interrupt Enable
Mnemonic: ME ENA
Type: R/W, 0
Multiple Interrupt Enable, when set, allows INTRs to be issued, if
enabled, upon the logging of every error detected by the DWMBB
regardless of the current state of Error Summary (XBER<31>). Self-
Test Fail (XBER<10>) does not affect Multiple Interrupt Enable.
The default for Multiple Interrupt Enable is not set, allowing one
interrupt to be issued, if enabled, upon detection of an error if Error
Summary (XBER<31>) is currently clear. If a subsequent error occurs,
a second interrupt is not issued while the first error is outstanding.
Software reads XBER after servicing the interrupt to ensure that all
errors have been detected.
bit<2>
Name: Reserved
Mnemonic: None
Type: RO, 0
Reserved; must be zero.
3–89