User`s guide

DWMBB/A Module Registers
Control and Status Register (ACSR)
bit<30>
Name: Control Reset
Mnemonic: CTL RESET
Type: WO, 0
Control Reset, when set, causes the DWMBB to execute a control reset
even if it is in a hung state or busy processing another transaction. A
control reset does the following:
• Resets all logic on the DWMBB/A module except the I/O registers
(including the PMRs) to an initialized (power-up) state. This
allows XMI operation to not be affected by the DWMBB/A module’s
reset.
• Resets the DWMBB/B module and the VAXBI.
• Disables IVINTRs by resetting IVINTR Enable (AIMR<31>).
Control Reset is only used for diagnostic purposes.
bit<29>
Name: PMR Ready
Mnemonic: None
Type: RO, 0
PMR Ready, when set, allows access of the PMRs from the XMI and
VAXBI for address translation. PMR control logic requires an 8.4-
ms period for the PMRs to initialize after power-up and node reset.
During this time, PMR Ready clears to prevent access of the PMRs
from the XMI and the VAXBI, disabling address translation. All I/O
references to the PMRs are NO ACKed when PMR Ready is clear.
System software sets PMR Ready and ensures that the PMRs are
properly set up before address translation is enabled.
bits<28:17>
Name: ECC Syndrome
Mnemonic: None
Type: RO, 0
The ECC Syndrome field is loaded and locked with the ECC syndrome
bits when an ECC error is detected. The field remains locked until
the error conditions are cleared. The ECC Syndrome field is valid if at
least one of the following bits is set:
• Correctable PMR ECC Error, AESR<13>
• Uncorrectable PMR ECC Error, AESR<12>
• Correctable DMA ECC Error, AESR<10>
• Uncorrectable DMA ECC Error, AESR<9>
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