User`s guide

DWMBB/A Module Registers

Diagnostic 1 Register (ADG1)

bit<1>

Name: Interrupt Sent Status

Mnemonic: INTR SENT

Type: R/W1C, 0

Interrupt Sent Status reﬂects the status of the XMI Error Bit Sent

signal, which is issued to the DWMBB/B module to generate an INTR.

Interrupt Sent Status is used by diagnostics in DWMBB/A module

loopback mode to ensure that the AIMR interrupt enable bits are

working properly. If an error condition occurs and its associated

interrupt enable bit is set in AIMR, Interrupt Sent Status sets.

Diagnostics then reads this bit to check that the interrupt would have

been sent to the DWMBB/B module because interrupts are disabled

during DWMBB/A module loopback mode.

Interrupt Sent Status is zero when not in DWMBB/A module loopback

mode. The DWMBB/A Multiple Errors (AESR<14>) bit is not affected

by the Self-Test Fail bit (XBER<10>).

bit<0>

Name: ECC Disable

Mnemonic: None

Type: R/W, 0

ECC Disable, when set, disables ECC detection and correction. The

four ECC status bits are forced to zero and no INTRs or IVINTRs are

generated. However, Force ECC Error (ADG1<11>) overrides ECC

Disable, so that if Force ECC Error is set, ECC errors are logged and

INTRs or IVINTRs are generated, regardless of the status of ECC

Disable.

NOTE: ECC Disable is for diagnostic purposes only and is not set

during normal operations. If ECC Disable is set during

normal operation, the integrity of DMA address translation

is compromised.

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