User`s guide

DWMBB/A Module Registers
Diagnostic 1 Register (ADG1)
When DWMBB/A Flip Failing Address Bit<1> is used with Force
DMA-A Buffer Busy (ADG1<5>) and Force DMA-B Buffer Busy
(ADG1<4>), both DMA data buffers can be thoroughly tested.
bit<8>
Name: DWMBB/A Flip Address Bit<29>
Mnemonic: DWMBB/A FLIP ADDR BIT<29>
Type: RO
DWMBB/A Flip Address Bit<29> causes I/O C/A bit<29> and the
C/A parity bit to be flipped for I/O transactions sent to the DWMBB
/B module. The transaction loops back to the DWMBB, where it is
processed as a DMA command.
bit<7>
Name: DWMBB/A Loopback Enable
Mnemonic: None
Type: R/W, 0
DWMBB/A Loopback Enable, when set, places the DWMBB/A module
into DWMBB/A module loopback mode. When this bit is used with
DWMBB/A Flip Address Bit<29> (ADG1<8>), I/O commands targeted
for the DWMBB/B module are converted into DMA commands for the
XMI.
When DWMBB/A Loopback Enable is set, the DWMBB/A module does
the following:
• Ignores the DWMBB/B module control signals
• Asserts its buffer full signals, preventing the DWMBB/B module
from sending DMA commands to the DWMBB/A module
• Disables its I/O buffer loaded signal, disabling any I/O commands
from being sent to the DWMBB/B module
• Disables interrupts
bit<6>
Name: Force Octaword Transfers
Mnemonic: FORCE OCTAWORD XFER
Type: R/W, 0
When Force Octaword Transfers is set, the DWMBB/A module
generates octaword DMA transactions regardless of the length code of
the original DMA transaction issued to the DWMBB. Force Octaword
Transfers is independent of operating modes.
CAUTION: Force Octaword Transfers is only used for diagnostic purposes.
If set during normal operation, undefined results occur.
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