User`s guide

DWMBB/A Module Registers
Diagnostic 1 Register (ADG1)
If Force Data NO ACK is set and a DMA read is received by the
DWMBB, the DWMBB times out after the DMA read command has
been issued on the XMI and before the DMA read data is returned,
causing NRR to set.
bit<26>
Name: Force Illegal Command
Mnemonic: FOR ILL CMD
Type: R/W, 0
Force Illegal Command, when set, forces an illegal (reserved) function
code of zero to be issued on the IBUS with a command/address cycle
that the DWMBB/A module accepts from the XMI and sends to the
DWMBB/B module, allowing diagnostic software to test Illegal CPU
Command (BESR<3>).
bits<25:14>
Name: Diagnostic ECC
Mnemonic: DIAG ECC
Type: R/W, 0
The contents of Diagnostic ECC, when Substitute ECC (ADG1<13>) is
set, is written to the PMR in place of the generated ECC. Diagnostic
ECC and Substitute ECC are used by diagnostic software to test the
ECC logic.
bit<13>
Name: Substitute ECC
Mnemonic: None
Type: R/W, 0
Substitute ECC, when set, causes the contents of Diagnostic ECC
(ADG1<25:14>) to be substituted for the ECC check bits when writing
to the ECC RAM.
bit<12>
Name: Latch Check Bits
Mnemonic: None
Type: R/W, 0
Latch Check Bits, when set, causes the Control and Status Register,
the ACSR, to log the ECC check bits stored in the RAMs, instead of
the syndrome bits, when an error is detected.
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