User`s guide

DWMBB/A Module Registers
Diagnostic 1 Register (ADG1)
bit<30>
Name: Receive Lockout Status
Mnemonic: RCV LOCKOUT STATUS
Type: R/W1C, 0
Receive Lockout Status sets on the first assertion of the XCI RECEIVE
LOCKOUT L signal. It can be cleared only after Force Transmit
Lockout (ADG1<10> is cleared.
bit<29>
Name: Transmit Lockout Status
Mnemonic: XMIT LOCKOUT STATUS
Type: R/W1C, 0
Transmit Lockout Status sets on the first assertion of the XCI
TRANSMIT LOCKOUT L signal.
bit<28>
Name: Error Summary Test
Mnemonic: ERR SUM TEST
Type: R/W, 0
Error Summary Test, when set, disables Self-Test Fail (XBER<10>)
from setting the Error Summary bit (XBER<31>), allowing diagnostic
software to test the Error Summary bit.
bit<27>
Name: Force Data NO ACK
Mnemonic: None
Type: R/W, 0
Force Data NO ACK, when set, forces the DWMBB to receive a NO
ACK confirmation instead of an ACK for DMA write data and I/O
read data cycles and also forces the DWMBB to time out waiting
for return DMA read data. These actions allow diagnostic software
to test RIDNACK (XBER<21>), WDNACK (XBER<20>), and NRR
(XBER<18>).
If Force Data NO ACK is set and either an I/O read command or
IDENT is received by the DWMBB, it is executed normally except
that the DWMBB receives a NO ACK confirmation on its data cycle,
causing RIDNAK to set.
If Force Data NO ACK is set and a DMA write is received by the
DWMBB, the DMA write is executed normally except that the
DWMBB receives a NO ACK confirmation on the last write data
cycle, causing WDNACK to set.
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