User`s guide

DWMBB/A Module Registers
Interrupt Mask Register (AIMR)
bit<31>
Name: Enable IVINTR Transactions
Mnemonic: None
Type: R/W, 0
When Enable IVINTR Transactions is set and IVINTR Destination
Register is properly configured, IVINTRs are enabled and can be
issued on the XMI bus. The following error conditions generate
IVINTRs:
• Invalid PFN, AESR<11>, only if the failing transaction was a DMA
write
• Uncorrectable DMA ECC error, AESR<9>, only if the failing
transaction was a DMA write
• Invalid VAXBI address, AESR<8>, only if the failing transaction
was a DMA write
• Internal Error, AESR<7>
• I/O Write Failure, AESR<6>
• BCI AC LO, AESR<5>
• IBUS DMA-A Data Parity Error, AESR<4>
• IBUS DMA-A C/A Parity Error, AESR<3>, only if the failing
transaction was a DMA write
• IBUS DMA-B Data Parity Error, AESR<2>
• IBUS DMA-B C/A Parity Error, AESR<1>, only if the failing
transaction was a DMA write
• Transaction Timeout, XBER<13>, only if the failing transaction
was a DMA write
CAUTION: Enable IVINTR Transactions MUST be set to ensure proper
error reporting in the case of asynchronous write failures and
to report the occurrence of a pending VAXBI power failure not
initiated by XMI AC LO, XMI DC LO, or an XMI node reset.
bits<30:28>
Name: Reserved
Mnemonic: None
Type: RO, 0
Reserved; must be zero.
3–65