User`s guide

DWMBB/A Module Registers
Error Summary Register (AESR)
If the transaction was a DMA write, or otherwise might cause a
data loss, an IVINTR with WRT ERROR INT set in the Type field is
generated if Enable IVINTR Transactions (AIMR<31>) is set.
bit<7>
Name: Internal Error
Mnemonic: None
Type: R/W1C, 0
The Internal Error bit sets to indicate that an UNEXPLAINED
internal error to the DWMBB/A module gate array was detected,
generally a hardware problem where control logic encountered
UNDEFINED conditions. The DWMBB/A module issues an IVINTR
transaction with WRT ERROR INT set in the Type field, if Enable
IVINTR Transactions (AIMR<31>) is set when Internal Error sets.
The following conditions cause the assertion of Internal Error:
• A state machine in the DWMBB/A module’s gate array reaches an
illogical state
• A parity error is detected internal to the gate array on the transfer
of PMR write data for a PMR write request. This means that the
PMR location’s data is corrupt and I/O Write Failure (AESR<6>)
also sets.
• A parity error is detected on the transfer of write data for a
loopback write command during a loopback mode. This also causes
the loopback write transaction to abort and I/O Write Failure
(AESR<6>) to set.
• A parity error is detected on the return of DMA read data that is
looped back as CPU read data during a loopback mode. This also
causes the loopback read transaction to abort.
bit<6>
Name: I/O Write Failure
Mnemonic: None
Type: R/W1C, 0
I/O Write Failure sets if the DWMBB/B module is unable to complete
an I/O write transaction to either its register space or to VAXBI
address space. Its assertion causes the generation of an IVINTR
transaction with WRT ERROR INT set in the Type field, if Enable
IVINTR Transactions (AIMR<31>) is set. Software uses this bit
and other error bits to determine the cause of a DWMBB-generated
IVINTR transaction.
When I/O Write Failure sets, the contents of the DWMBB/A’s
Responder Error Address Register lock.
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