User`s guide

DWMBB/A Module Registers
Error Summary Register (AESR)
bit<10>
Name: Correctable DMA ECC Error
Mnemonic: CORR DMA ECC ERR
Type: R/W1C, 0
CORR DMA ECC ERR indicates, when set, that a fetch from the PMR
during a DMA address translation detected and corrected an error.
The assertion of this bit locks the ABEAR. CORR DMA ECC ERR sets
only when the DWMBB is operating in an address translation mode.
When this bit sets, an interrupt is generated if INTR CORR ECC ERR
(AIMR<10>) is set.
bit<9>
Name: Uncorrectable DMA ECC Error
Mnemonic: UNCORR DMA ECC ERR
Type: R/W1C, 0
UNCORR DMA ECC ERR indicates, when set, that a fetch from the
PMR during a DMA address translation detected an uncorrectable
error. The assertion of this bit locks the ABEAR. UNCORR DMA
ECC ERR sets only when the DWMBB is operating in an address
translation mode. When this bit sets, an interrupt is generated if
INTR UNCORR ECC ERR (AIMR<9>) is set.
If the transaction was a DMA write, or otherwise might cause a
data loss, an IVINTR is generated if Enable IVINTR Transactions
(AIMR<31>) is set.
bit<8>
Name: Invalid VAXBI Address
Mnemonic: INV BI ADR
Type: R/W1C, 0
INV BI ADR indicates, when set, that the VAXBI address for the
requested DMA transaction is invalid (not in memory space).
In DWMBA compatibility mode or 40-bit address translation mode
using 8-Kbyte page size, a DMA transaction is invalid if VAXBI
address bit <29> equals one.
In 40-bit address translation mode using 4-Kbyte page size, a DMA
transaction is invalid if VAXBI address bits <29:28> do not equal zero.
In 40-bit address translation mode, a DMA transaction is invalid if
VAXBI address bits <28:25> do not equal zero.
The assertion of INV BI ADR causes the ABEAR to lock the VAXBI
address of the failed transaction. An interrupt request is generated if
INTR INV BI ADR (AIMR<8>) is set.
3–59