User`s guide

DWMBB/A Module Registers
Error Summary Register (AESR)
bit<13>
Name: Correctable PMR ECC Error
Mnemonic: CORR PMR ECC ERR
Type: R/W1C, 0
CORR PMR ECC ERR indicates, when set, that a correctable ECC
error occurred during an I/O read access to a PMR. The assertion
of this bit locks the Responder Error Address Register (AREAR). If
a PMR location is read during DWMBA compatibility mode and a
correctable error is detected, this bit sets, a CRD response is returned
to the XMI commander, and an interrupt is generated if INTR CORR
ECC ERR (AIMR<10>) is set.
bit<12>
Name: Uncorrectable PMR ECC Error
Mnemonic: UNCORR PMR ECC ERR
Type: R/W1C, 0
UNCORR PMR ECC ERR indicates, when set, that an uncorrectable
ECC error occurred during an I/O read access to a PMR. The assertion
of this bit locks the Responder Error Address Register (AREAR). If
a PMR location is read during DWMBA compatibility mode and an
uncorrectable error is detected, this bit sets, an RER is returned to
the XMI commander, and an interrupt is generated if INTR UNCORR
ECC ERR (AIMR<9>) is set.
bit<11>
Name: Invalid PFN
Mnemonic: IPFN
Type: R/W1C, 0
IPFN indicates, when set, that the Valid bit of a PMRE accessed
during a DMA transaction was not a one. The assertion of IPFN
causes the VAXBI Error Address Register (ABEAR) to lock the VAXBI
address of the failed DMA transaction and an interrupt request is
generated if INTR IPFN (AIMR<11>) is set.
If the transaction was a DMA write, or otherwise might cause a
data loss, an IVINTR is generated if Enable IVINTR Transactions
(AIMR<31>) is set.
3–58