User`s guide

DWMBB/A Module Registers
Bus Error Register (XBER)
bit<31>
Name: Error Summary
Mnemonic: ES
Type: RO, 1
ES represents the logical OR of the error bits in this register.
Therefore, ES asserts whenever any error bit listed below asserts:
XBER Bit Mnemonic Name
<27> CC Corrected Confirmation
<24> IPE Inconsistent Parity Error
<23> PE Parity Error
<22> WSE Write Sequence Error
<21> RIDNAK Read/IDENT Data NO ACK
<20> WDNAK Write Data NO ACK
<19> CRD Corrected Read Data
<18> NRR No Read Response
<17> RSE Read Sequence Error
<16> RER Read Error Response
<15> CNAK Command NO ACK
<13> TTO Transaction Timeout
<12> NSES Node-Specific Error Summary
<10> STF Self-Test Fail
bit<30>
Name: Node Reset
Mnemonic: NRST
Type: R/W, 0
Writing a one to NRST initiates a power-up reset of the node. Reads to
this bit location return zero. When NRST has a one written to it, the
DWMBB:
• Resets all logic on the DWMBB/A module to an initialized (power-
up) state, regardless of what state it is in.
• Asserts the RESET control signal to the DWMBB/B module,
which causes the assertion of BI AC LO L and BI DC LO L. The
assertion of BI DC LO L causes the DWMBB/B module to reset to
an initialized (power-up) state.
During the time that the DWMBB is performing its node reset, it does
not affect the operation of the XMI bus.
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