User`s guide

DWMBB Adapter
Table 3–11 VAXBI Registers
Name Mnemonic Address
1
Device Register DTYPE
2
bb + 0000 0000
VAXBI Control and Status Register VAXBICSR bb + 0000 0004
Bus Error Register BER bb + 0000 0008
Error Interrupt Control Register EINTRSCR bb + 0000 000C
Interrupt Destination Register INTRDES bb + 0000 0010
IPINTR Mask Register IPINTRMSK bb + 0000 0014
Force-Bit IPINTR/STOP Destination Register FIPSDES bb + 0000 0018
IPINTR Source Register IPINTRSRC bb + 0000 001C
Starting Address Register SADR bb + 0000 0020
Ending Address Register EADR bb + 0000 0024
BCI Control and Status Register BCICSR bb + 0000 0028
Write Status Register WSTAT bb + 0000 002C
Force-Bit IPINTR/STOP Command Register FIPSCMD bb + 0000 0030
User Interface Interrupt Control Register UINTRCSR bb + 0000 0040
General Purpose Register 0 GPR0 bb + 0000 00F0
General Purpose Register 1 GPR1 bb + 0000 00F4
General Purpose Register 2 GPR2 bb + 0000 00F8
General Purpose Register 3 GPR3 bb + 0000 00FC
Slave-Only Status Register SOSR bb + 0000 0100
Receive Console Data Register RXCD bb + 0000 0200
1
The abbreviation "bb" refers to the base address of a VAXBI node (the address of the
first location of I/O adapter address space).
2
Described in this section.
Table 3–12 Types of Registers and Bits
Type Description
0 Initialized to logic level zero
1 Initialized to logic level one
X Initialized to either logic level
RO Read only
R/W Read/write
R/Cleared on W Read/cleared on write
R/W1C Read/cleared by writing a one
MBZ Must be zero
3–42