User`s guide

DWMBB Adapter

3.10 ECC Protection on the PMR Data Path

The DWMBB can correct single-bit errors and detect double-bit

errors on Page Map Registers. If errors come from a single 4-bit

RAM, one to four bits can be corrected.

Figure 3–13 Page Map Register Organization

Error

Page Map Register Correction Code

103478 03 78

64K

msb−p095−89

RAM 4 RAM 5 RAM 6 RAM 7 RAM 8RAM 1 RAM 2 RAM 3 RAM 9 RAM 11RAM 10

The page map registers are organized with eight 4-bit x 64 K RAMs for

the page map data and three 4-bit x 64 K RAMs for the error correction

code (ECC), as shown in Figure 3–13.

Error correction code on the page map register data path allows the

DWMBB/A module to detect and correct from one to four failed bits within

a single 4-bit wide RAM. Up to eight failed bits across two RAMS are

detected but not corrected.

The PMRs are always read or written as 32-bit registers. During PMR

I/O write transactions, the DWMBB/A module generates a 12-bit error

correction code and writes this code, with the 32 data bits, into the PMR

location being addressed.

During PMR I/O read transactions or DMA address translations, the

DWMBB/A module reads the data and ECC bits out of the PMRs. The

data and ECC ﬁelds are checked for errors. If an error is detected,

correctable or uncorrectable, it is logged and an interrupt is issued, if

enabled.

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