User`s guide

DWMBB Adapter
3.4.3 Interprocessor Interrupts
Interprocessor Interrupts (IPINTRs) are generated by VAXBI nodes
targeting the DWMBB. Software must set up the IPINTR Mask Register
and the IPINTREN bit in the BCI Control and Status Register. An
Interprocessor Interrupt puts a level 6 interrupt onto the VAXBI. The
BIIC Interrupt Destination Register causes the interrupt that is received
by the DWMBB/B module as a generic VAXBI level 6 interrupt to be
passed to the XMI with an IPL of 16 (hex). When the DWMBB/B module
receives an IDENT transaction from the XMI, it issues the IDENT on the
VAXBI. If no other level 6 interrupts are pending on the VAXBI, the BIIC
issues the vector from its User Interface Interrupt Control Register.
The interprocessor interrupt vector value written into the UINTRCSR is
treated by the DWMBB as a generic VAXBI interrupt. If bits <13:9> of the
vector are zero, the DWMBB concatenates the contents of the BVOR with
bits <8:0> of the vector.
3.4.4 Interrupt Transactions
Interrupts (INTRs) are generated by the DWMBB when a status change
or error condition occurs. Interrupts are also generated by VAXBI devices
and are translated into the appropriate XMI interrupt transactions as they
pass through the DWMBB to the XMI.
If both DWMBB and VAXBI device interrupts are pending at the same IPL
when an XMI IDENT transaction is issued, the DWMBB returns its vector
first to ensure that DWMBB error interrupts are serviced first.
3.4.4.1 DWMBB Adapter-Generated Interrupts
Errors detected by the DWMBB cause bits to be set in the Bus Error
Register and Error Summary Register (AESR and BESR). If the
corresponding interrupt mask bits are enabled, a level 7 interrupt (IPL 17
(hex)) is requested by the DWMBB. The DWMBB error interrupt request
is cleared when an XMI IDENT transaction is received at IPL 17.
3.4.4.2 VAXBI-Generated Interrupts
Interrupt transactions directed to the DWMBB from the VAXBI are
handled by the BIIC. It logs the acceptance of the interrupt transaction
at the corresponding level and issues an XMI interrupt command. The
interrupt request is cleared when an XMI IDENT transaction is received
at the corresponding IPL.
3.4.4.3 BIIC-Generated VAXBI Interrupts
The BIIC generates interrupt transactions to the VAXBI in response
to errors it detects on the VAXBI. The user controls the generation of
interrupts with the BIIC’s Error Interrupt Control Register. INTRDES is
configured so that the interrupt is received by the DWMBB/B module as
a VAXBI interrupt. This interrupt is passed through the DWMBB to the
XMI to inform an XMI commander of bus errors on the VAXBI.
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